In information processing apparatuses that include a CPU such as a microprocessor, a DRAM is often used for storage of data for executing an OS and various applications, and for temporary storage of data for executing image processing. The DRAM is connected to a CPU, an SoC (System on a Chip), or the like and used by them. Furthermore, in recent years, as functions have been added/enhanced in information processing apparatuses, the amount of memory bandwidth needed in DRAMs has increased. Because of this, the amount of memory bandwidth has been increased by raising the clock frequency during memory access, according to a standard such as DDR3 or DDR4. Furthermore, as another method, memory bandwidth is reserved by including multiple DRAM channels that are connected to a CPU or an ASIC (Application Specific Integrated Circuit). However, a new problem occurs in that increasing the clock frequency and employing multiple memory channels increases power consumption.
In view of this, wide IOs, which are a next-generation DRAM standard, are currently gaining attention. A wide IO is configured by placing a DRAM chip over an SoC die using a 3D stacking technique based on TSVs (Through-Silicon Vias). Features of the wide IO include being able to obtain a wide bandwidth that is over 12.8 GB/s (gigabytes per second) at most, with a wide data width of 512 bits, and having low power consumption due to the access frequency being suppressed to a low frequency. Also, by employing TSVs, the package size can be made thinner and smaller compared to a conventional PoP (Package on Package). Furthermore, in this configuration, a data width of 512 bits is divided into four 128-bit channels and each channel is controlled individually. For example, a method of use is possible in which channel 1 and channel 2 are put in a self-refresh state, while channel 3 and channel 4 are used for normal memory access, or the like. A basic structure and basic access method for such a wide IO is disclosed in US2012/0018885.
In the stacked structure of a wide IO, stacking chips in an SoC package causes structural susceptibility to heat, and therefore problems related to heat generation arise more often than with conventional DRAMs. As a countermeasure, it has become standard for the wide IO to build temperature sensors for detecting memory temperatures into chips, and the self-refresh rate can be controlled according to the temperatures detected by the temperature sensors.
Additionally, in a chip stacked in compliance with wide IO standards, the temperatures of locations at which temperatures are highest on the chip (hereinafter referred to as “hotspots”) are higher than in the case of using a conventional chip. It is known that this increases the difference in temperature between the temperatures of hotspots and non-hotspots. Because of this, for example, in the case where a hotspot appears at a location that is different from the location of a temperature sensor on the chip, there is a possibility that a large difference will occur between the temperature detected by the temperature sensor and the temperature of the hotspot. As a result, in the case where the self-refresh rate has been set according to the temperature detected by the temperature sensor, there is a possibility that the hotspot will lead to the loss of content stored in the DRAM and an increase in power consumption.
In order to deal with this phenomenon, a value called a “thermal offset” that indicates a difference in temperature between hotspots and locations at which temperature sensors have been provided is defined as a standard. The thermal offset value is set in steps to match the difference in temperature between the hotspots and the locations at which temperature sensors are provided. By setting the self-refresh rate based on the thermal offset value that was set with this standard, self-refresh rate control giving consideration to this temperature difference is realized.
However, it is not easy to appropriately set the thermal offset by appropriately estimating the difference in temperature between temperatures of hotspots and temperatures detected by temperature sensors. This is because the locations and temperatures of the hotspots on the chip change moment by moment depending on the operating state of the wide IO memory device, which changes according to the state of memory access with respect to the wide IO memory device and the processing state of the SoC die. Because of this, it is necessary to appropriately set the thermal offset with consideration given to the operating state of the wide IO memory device.